Network element for signals of the optical transport network (OTN)

ABSTRACT

A crossconnect for asynchronous OTN signals operates synchronously internally at an internal clock rate. Received OTN signals are synchronized to an internal frame format by stuffing. The synchronized signals are parallelized and switched with a switching matrix comprising synchronously operating integrated circuits that operate at the internal clock rate. At the output, the synchronized signals are again destuffed and are transmitted again at the original bit rate.

[0001] The invention is based on a priority application EP 01 440 232.5 which is hereby incorporated by reference.

FIELD OF THE INVENTION

[0002] The invention relates to a network element for asynchronous optical communications signals that have been assembled in accordance with a multiplex specification for optical transport networks (OTNs).

BACKGROUND OF THE INVENTION

[0003] The International Telecommunication Union has specified interfaces for a new transport network having the designation OTN (optical transport network) in its new recommendations ITU-T G.709 (Prepublished Recommendation, February 2001) which is incorporated by reference herein. Said new transport network serves the high-speed transmission of digital optical signals in future WDM (wavelength-division multiplex) networks. In contrast to previous transport networks, such as SDH (synchronous digital hierarchy) networks and SONET (synchronous optical network), OTN operates with substantially asynchronous optical signals. This means that the individual communications signals are not synchronized to a common network timing and may have different bit rates within a specified range (±20 ppm).

[0004] For said novel transport network, network elements now have to be developed that are capable of switching the newly specified communications signals. Said network elements are, in particular, optical crossconnects and add/drop multiplexers. The essential feature of such network elements is a switching matrix that switches communications signals from any to any port in an arbitrary controlled manner.

[0005] Since OTN is an optical transport network, the use of a purely optical switching matrix would suggest itself in network elements. Such a matrix makes it possible to switch so-called OTUk signals (optical channel transport unit, k=1, 2 or 3). Such OTUk signals are characterized by their frame structure, bit rate and bandwidth. At present, available, purely optical switching matrices require, however, a number of optical amplifiers and repeaters and are therefore technically very complex and expensive, they suffer from limited capacity and reliability and they are bulky. In addition, it will be necessary to evaluate and to terminate certain information in the transport frames of the communications signals, which inevitably requires electrical processing.

[0006] Alternatively, an asynchronous electrical switching matrix is suitable, i.e. a switching matrix that is made up of a multiplicity of electrical switching circuits which make it possible to switch electrical signals of any bit rate in a certain bandwidth range. Such integrated circuits are, however, only being developed and are at present not yet available. The high bit rates of the OTN signals (2.67 Gbit/sec, 10.71 Gbit/sec and 43.12 Gbit/sec) present the development of such synchronously operating integrated circuits with major technical problems.

SUMMARY OF THE INVENTION

[0007] The object of the present invention is therefore to specify a network element for switching asynchronous optical communications signals, which network element can be easily and reliably implemented with current means.

[0008] The object is achieved by a network element for asynchronous optical communications signals that are assembled in accordance with a multiplex specification and have a bit rate within a specified bit-rate range. The network element has O/E converters for converting received optical signals into electrical signals, stuffing devices for adapting the bit rates of the electrical signals to an integral multiple of an internal clock rate that is higher than the upper limit of the specified bit-rate range, serial/parallel converters for converting the stuffed signals into a specified number of parallel signals having the internal clock rate, and a synchronous electrical switching matrix that operates at the internal clock rate for switching the parallel signals from any to any port.

[0009] Advantageous refinements are to be found in the dependent claims.

[0010] Advantages of the invention are that it makes use of ASIC technology that has been tried and tested over many years and can therefore be immediately made ready for the market and that it makes possible a fractional switching of signals of higher bit rates. It is even possible to upgrade existing installations for OTN in accordance with the invention without a new type of matrix having to be incorporated. A particular advantage is, in addition, that the invention makes possible a hit-less switch-over between redundant matrix assemblies.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The invention is explained below by reference to the sole figure in an exemplary embodiment. The figure shows a block circuit diagram of a network element according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0012] A basic idea of the invention is to synchronize the received asynchronous communications signals to an internal frame format having a slightly higher internal clock rate by stuffing. The signals thus synchronized are parallelized and switched with a standard switching matrix comprising synchronously operating integrated circuits that operate at the internal clock rate.

[0013] An optical crossconnect operating according to this principle is shown diagrammatically in the figure. The received optical communications signals are converted (not shown) by O/E converters into electrical signals 20, 23, 26 and fed to a stuffing device 21, 24, 27 herein referred to as mappers. The mappers are each connected to serial/parallel converters 22, 25, 28. The serial/parallel converters are connected via parallel connections to a synchronously operating electrical switching matrix 10. At the output, the switching matrix 10 is followed again by parallel/serial converters 32, 35, 38 that are each connected to a destuffing device 31, 34, 37 herein referred to as a demapper. The output signals of the demappers are asynchronous communications signals 30, 33, 36 having the original bit rate again. The electrical output signals 30, 33, 36 are then converted into optical communications signals in E/O converters (not shown) and fed into the optical transport network.

[0014] The figure shows, by way of example, only one input and one output for each multiplex level (OTU1, OTU2, OTU3). In reality, however, the crossconnect has a multiplicity of inputs and outputs for each of the multiplex levels. The mappers and demappers shown as spatially separated in the figure may also be disposed in pairs on a respective I/O card.

[0015] The optical crossconnect has a timing system with an oscillator 15 whose output clock f₀ is fed to a plurality of dividers. The undivided clock (corresponding to a divider ratio of 1/1) is fed to the third mapper 21 and demapper 31. A first divider 16 having a divider ratio of 4/1 generates a clock signal f₀/4 that has one quarter of the original clock rate and is fed to the second mapper and demapper 24, 34. A second divider 17 that has a divider ratio of 16/1 generates a clock signal f₀/16 that has a 16^(th) of the original clock rate and is fed to the first mapper and demapper 27, 37. A third divider 18 having a divider ratio of N/1 generates a clock signal f₀/N which is fed to the serial/parallel converters 22, 25, 28, the parallel/serial converters 32, 35, 38 and the switching matrix 10. N is equal to 16 times the parallelization factor of the serial/parallel converter 28. The clock signal f₀/N provides the internal clock rate at which the matrix operates.

[0016] For the invention it is not necessary that a true clock division take place. On the contrary, a suitable gapped clock also fulfils the requirements. Thus, a 4:1 divider can be designed so that it allows through only every fourth clock pulse and blocks the other three clock pulses in each cycle.

[0017] The function of the optical crossconnect is as follows. The frequency of the oscillator 15 is 43.02+ε GHz, where ε is the value to be chosen by which the internal clock frequency is higher than the maximum bit rate of the received asynchronous signals. The frame format and ε are chosen in such a way that the resultant stuffing rate is between 0 and 1.

[0018] The first mapper 27 receives a communications signal of the lowest OTN hierarchy level. This is described as OTU1 (optical channel transport unit) and has a nominal bit rate of 2.7 Gbit/sec. The oscillator frequency is divided by 16 in order to generate a clock signal f₀/16 having a slightly higher clock rate. The OTU1 signal is synchronized to this clock rate. For this purpose, an internal proprietary frame format is formed from the OTU1 signal by filling it up to the clock rate of the clock signal f₀/16 by stuffing. Additional bit positions of this internal frame format indicate the start of the frame and how many stuffing bits are attached to the data signal. The stuffing can be performed bitwise or bytewise and can operate both according to the positive/zero/negative stuffing method and according to the positive stuffing method. Positive stuffing, however, is preferred here since it results in lower stuffing jitter.

[0019] The synchronized internal signals are then parallelized with the serial/parallel converter 28 and fed to the switching matrix 10. In the exemplary embodiment shown, the synchronized internal signal, which corresponds to the multiplex level OTU1, is parallelized four-fold. The internal clock rate at which the integrated circuits of the switching matrix operate is consequently 670 MHz. The clock frequency for switching matrix 10 and serial/parallel converter is generated by dividing the frequency of the oscillator by 64, i.e. N=4 in the figure.

[0020] For the multiplex level OTU2, the frequency of the oscillator is divided by 4 and fed to the mapper 24 in order to synchronize the received OTU2 signal thereto. The synchronized signal is then parallelized sixteen-fold in the serial/parallel converter 25 and fed to the switching matrix 10 via 16 connections.

[0021] For the multiplex level OTU3, the frequency of the oscillator is fed undivided to the mapper 21 and the received OTU3 signal is synchronized thereto. The synchronized signal is parallelized sixty-four-fold in the serial/parallel converter 22 and fed to the switching matrix 10 via 64 connections.

[0022] The parallelized internal signals are switched on parallel paths through the switching matrix 10, i.e. for an OTU1 signal, 4 paths are switched through the matrix, for an OTU2 signal, 16 are switched and for a OTU3 signal, 64 are switched.

[0023] The oscillator 15 may be an oscillator having a precision of ±20 ppm or less. Since the bandwidth specified for OTN is ±20 ppm, a frequency difference of ±40 ppm would have to be made up for by stuffing in the most unfavorable case. If a correspondingly more precise oscillator were used, it would still be at least ±20 ppm. Synchronization of the oscillator to an external clock is unnecessary, but may be performed, for example, to synchronize all the network elements of a network node to the same internal clock.

[0024] The switching matrix 10 comprises integrated circuits, known per se, that operate and switch synchronously at the internal clock rate. The integrated circuits may, for example, be ASICs (application specific integrated circuits), which, according to matrix size, are arranged to form a square matrix or to form a three-stage or multi-stage Clos matrix.

[0025] The function of the demapper is to remove the frames and stuffing bits added in the mapper and to reproduce the communications signals at the original bit rate.

[0026] Preferably, the demappers contain a clock filter to filter stuffing jitter.

[0027] A multiplicity of modifications of the structure described for the crossconnect are possible, of which the following may not be a final enumeration.

[0028] Instead of all the three multiplex levels standardized in G.709, only one or two levels may be supported. Thus, for example, a crossconnect may support only OTU1 or only OTU2 signals or OTU1 and OTU2 signals, but no OTU3 signals.

[0029] The switching matrix may operate, for example, at an internal clock rate that corresponds to the clock to which the OTU1 signals are synchronized. The corresponding synchronized internal OTU1 signals are then no longer parallelized, but only the synchronized internal OTU2 and OTU3 signals (degree of parallelization for OTU1 is 1).

[0030] The dividers may be cascaded, for example instead of a 16:1 divider, the clock divided by 4 can be divided again by 4.

[0031] Instead of a divided clock, a gapped clock can also be generated.

[0032] A preferred embodiment of the invention uses the clock rate, well known from SDH network elements, of STM-1 (synchronous transport module) of 155.52 MHz as internal clock for the switching matrix. The parallelization is consequently for

[0033] STM-1: 1 timeslot

[0034] STM-4: 4 timeslots

[0035] STM-16: 16 timeslots

[0036] STM-64: 64 timeslots

[0037] OTU1: 18 timeslots

[0038] OTU2: 72 timeslots and for

[0039] OTU3: 288 timeslots.

[0040] The maximum frequency the oscillator generates is 288*155,520 kHz=44.79 GHz. This is about 5% above the clock rate of OTU3. For electrical processing, this clock rate is near the technical limit. The crossconnect can therefore also be designed for OTU2 and with a maximum clock rate of 72*155,520 kHz=11.20 GHz.

[0041] The frame format for OTN signals is chosen as follows: The frame length is 1000 bits; other lengths are, however, equally possible. Part thereof is overhead bits plus a stuffing bit and, to be specific:

[0042] For OTU1: 47 overhead bits+1 stuffing bit; the nominal stuffing rate is 0.61905 (min=0.58095, max=0.65714);

[0043] For OTU2: 43 overhead bits+1 stuffing bit; the nominal stuffing rate is 0.60056 (min=0.56231, max=0.63882);

[0044] For OTU3: 39 overhead bits+1 stuffing bit; the nominal stuffing rate is 0.54802 (min=0.50960, max=0.58643).

[0045] Of the overhead bits, 16 bits are used as frame alignment signal, similar to the A1, A2 bytes in the STM-N frame in the case of SDH. The remaining overhead bits are used for stuffing identification and also internal maintenance and monitoring purposes. Unused overhead bits are filled with fixed stuffing bits (fixed stuff).

[0046] OTU3 signals are divided into 40 blocks of 24 data bits each and one overhead bit. OTU2 and OTU3 signals are 4 or 8 blocks respectively, to form 23 data bits and 2 overhead bits in each case therefrom. Advantages of this configuration are:

[0047] the frame repetition frequency is high, as a result of which stuffing jitter can be filtered well;

[0048] the overhead bits are uniformly distributed, as a result of which only slight stuffing jitter occurs; and

[0049] internal additional bits are available for maintenance.

[0050] If, according to the invention, a positive/zero/negative stuffing method is used to adapt the received communications signals to the internal clock rate, the internal frame format contains a negative stuffing opportunity bit occupied by way of exception with a data bit (negative stuffing) and also a positive stuffing opportunity bit occupied by way of exception with a stuffing bit (positive stuffing).

[0051] A further modification of the crossconnect according to the invention is that, in the mappers, instead of the OTUk signals, the ODUk signals (optical channel data unit) contained therein are stuffed to correspondingly lower internal bit rates. OTUk is distinguished from ODUk by an additional OTUk overhead and also bits for FEC (forward error correction). Said additional overhead and FEC bits can be terminated in the mappers and evaluated. The bit rates for ODUk are approximately 2.50 Gbit/sec for ODU1, 10.04 Gbit/sec for ODU2 and 40.32 Gbit/sec for ODU3.

[0052] The switching matrix of the network element may be designed in redundant form, i.e. contain an active switching matrix and a redundant switching matrix for the fault condition. In this case, the invention makes possible, because of the internal synchronization, an hit-less switchover between the two copies of the switching matrix. 

What is claimed is
 1. A network element for asynchronous optical communications signals that are assembled in accordance with a multiplex specification and have a bit rate within a specified bit-rate range, comprising O/E converters for converting received optical signals into electrical signals; stuffing devices for adapting the bit rates of the electrical signals to an integral multiple of an internal clock rate that is higher than the upper limit of the specified bit-rate range; serial/parallel converters for converting the stuffed signals into a specified number of parallel signals having the internal clock rate and a synchronous electrical switching matrix that operates at the internal clock rate for switching the parallel signals from any to any port.
 2. A network element according to claim 1 that is designed as an optical crossconnect.
 3. A network element according to claim 1, which is designed for optical communication signals in accordance with ITU-T G.709.
 4. A network element according to claim 1 having a second redundant switching matrix to which the first switching matrix is switched over in an interruption-free manner in the fault condition.
 5. A network element according to claim 1, wherein the internal clock frequency is chosen in such a way that the stuffing rate is between 0 and
 1. 6. A network element according to claim 1, having a clock generator for generating a clock signal that is an integral multiple of the internal clock rate, and having a divider for generating the internal clock signal.
 7. A network element according to claim 6, wherein the clock generator is a free-running oscillator having a frequency position of about ±20 ppm or less.
 8. A network element according to claim 6, wherein the clock generator can be externally synchronized.
 9. A network element according to claim 6, wherein the divider generates a gapped clock having the internal clock rate by blocking individual clock pulses of the clock signal generated by the clock generator.
 10. A network element according to claim 6, comprising first stuffing devices for adapting the bit rates of electrical signals of a lower hierarchy level to a first integral multiple including 1 of the internal clock rate and second stuffing devices for adapting the bit rates of the electrical signals of a middle hierarchy level to a second integral multiple of the internal clock rate, which is greater than the first multiple.
 11. A network element according to claim 10, wherein the lowest multiplex level corresponds to OTU1 and the middle multiplex level to OTU2 in accordance with ITU-T G.709.
 12. A network element according to claim 10, comprising a third stuffing device for adapting the bit rates of electrical signals of a highest hierarchy level to a third integral multiple of the internal clock rate that is greater than the second multiple.
 13. A method of switching asynchronous optical communications signals that are assembled in accordance with a multiplex specification and have a bit rate within a specified bit-rate range, comprising the following steps: converting of received optical signals into electrical signals; p1 adapting of the bit rates of the electrical signals by stuffing to an integral multiple of an internal clock rate, which multiple is higher than the upper limit of the specified bit-rate range; converting the stuffed signals into a specified number of parallel signals having the internal clock rate and switching the parallel signals with a synchronous electrical switching matrix that operates at the internal clock rate from any to any port in an arbitrary controlled manner. 